1. Technical Field
The present invention relates to a memory control apparatus and a generation method of an error correcting code for data to be written into a cache memory.
2. Description of the Related Art
It has come into practice to store, in a cache memory, data read out from a main memory so as to accelerate the processing speed of a CPU by accessing the data in the cache memory. An error correcting code is attached to the data in the cache memory in order to protect the data.
Patent Document 1 describes writing, into a memory, pieces of data having a size smaller than the data width from which a check bit can be generated, by merging the pieces of data into a single piece of data using a multiplexer, generating a check bit from the data using an ECC generation unit, and writing it into the memory. It has an effect of shortening the access time with a read-modify-write action in a partial write operation.
Patent Document 2 describes a partial write action crossing a double-word boundary, performed by storing data from a channel in a swap buffer when there is no corresponding address in a cache, merging a double-word related to the partial write action and the data from the channel in the swap buffer, and writing it into a main memory.
FIG. 16 is a diagram describing a conventional of an error correcting code generation method in a memory system comprising a data RAM and an ECCRAM.
When an instruction processing unit (not shown in the figure) outputs a store instruction, whether or not data to be stored exists in a data RAM (cache memory) 13 is checked. When the data to be stored exists, 8-byte data including the data to be stored is read out and checked for an error. At this time, the store data corresponding to the store instruction is written into a store buffer STB 11.
Next, when the instruction processing unit issues a store permission, the data in the store buffer STB 11 is written into a write buffer WB 12, and the data is further written into the data RAM 13. At the same time with the writing, 8-byte data is read out from the data RAM 13, and an error correcting code ECC 1 is generated from the data stored in a non-target area in the is 8-byte data. Another error correcting code ECC2 is then generated from the data stored in the target area in the 8-byte data. The two ECCs are merged to generate an error correcting code ECC for the stored and updated data, and the generated ECC is stored in an ECC RAM 14.
The conventional error correcting code generation method described above has the following problems.
When an error is not detected in the error check performed when the cache memory is searched in response to a store instruction, and detected in the error check performed for the data read out after the data is written into the cache memory, an error correcting code for the data after the writing cannot be generated appropriately. The error correcting code stored in the ECCRAM 14 is the one generated from the data before the store instruction is realized, and the data before the realization of the store instruction no longer exists at this time. Therefore, there occurs an error that even when an error is detected, it is impossible to correct the 1-bit error in the data.
One of the causes of the error described above is that in the case of writing and readout to/from a SRAM (Static Random Access Memory), when the readout is performed immediately after the writing, the data in the state immediately before the readout remains on a bit line, decreasing the readout margin of the next cycle. The structure is designed in such a way that the bit line is charged up to the power voltage VDD within a predetermined time using a precharge transistor, so that data does not remain after the writing. Specifically, the writing into a memory cell is performed while setting, to a low level, one in a bit line pair connected to the memory cell. After the completion of the writing, the written data is purged before the start of writing in the next cycle, by shorting the bit line pair at the power voltage VDD.
However, an error occur with the readout in the next cycle, when the SRAM is operated at an operation cycle exceeding the originally designed cycle, or when the bit line pair cannot be precharged up to the power voltage VDD due to the poor characteristic of the precharge transistor caused by the variation in the manufacture quality of the transistor.    [Patent Document 1] Japanese Unexamined Patent Application Publication No. 10-232789    [Patent Document 2] Japanese Examined Patent Application Publication No. 58-21353